1. Field
The various circuit embodiments described herein relate in general to electronic switches, and, more specifically, to electronic switch architectures that can operate at low supply voltages.
2. Background
Electronic switches are found in many electronic applications. For example analog-to-digital converters (ADCs), or the like, is one application in which electronic switches are widely used. Many other general applications abound. An example of a complementary metal-oxide semiconductor (CMOS) switch 10 of one type of electronic switch described herein is shown in FIG. 1, to which reference is now made.
The switch 10 includes a p-channel metal-oxide semiconductor MOS (PMOS) device 12 and an n-channel metal-oxide semiconductor (NMOS) device 14. The PMOS device 12 has its source connected to an input node 16 and its drain connected to an output node 18. The gate of the PMOS device 12 is connected to a reference potential, or ground 22. The NMOS device 14 has its drain connected to the input node 16 and its source connected to the output node 18. The gate of the NMOS device 14 is connected to an analog voltage supply source (VDD) 22.
In operation, when the voltage between the input node 16 and ground 20 is above Vtp (Vtp is the threshold voltage of the PMOS device 12), the PMOS device 12 will conduct. Similarly, when the voltage between VDD 22 and the input node 16 is above the threshold voltage Vtn of the NMOS device 14, the NMOS device 14 will conduct.
One of the conditions that is often encountered is a high rail-to-rail signal voltage. A high supply range between 1.7 V and 3.6 V must be supported in many applications. However, the case of a CMOS switch, the threshold voltage of the PMOS device 12 plus the threshold voltage of the NMOS device 14 (Vtp+Vtn) may be higher than the difference in voltage between VDD and ground. As a result, a large switch area may be required. Another condition that may be encountered in some applications is that a supply boost switch may be unusable due to a very large clock time period, or a unavailable usable clock signal.
In many applications, the switch may be operated with a sampling signal, such as, for instance, in the example CMOS switch circuit 30 shown in FIG. 2, to which reference is now additionally made. The CMOS switch circuit 30 includes an NMOS device 34 and a PMOS device 36 between the input node 38 and output node 40. A variable voltage 32 is applied to the input node 38. The sampling signal (SAMP) is applied to the gate of the NMOS device 34 and an inverted sampling signal (SAMPZ) is applied to the gate of the PMOS device 36. The output from the switch 30 is applied across a capacitor 42 in the output node 40 and connected to an output by a switch 44 that is switched at a sampling frequency.
However, in many applications, for example in analog-to-digital converters (ADCs), a sampling instant 45 may be provided by an off-chip signal that is asynchronous to an internal analog-to-digital (ADC) conversion clock 46. Synchronizing the off-chip asynchronous sampling clock to an internal ADC clock and using that to operate a boost switch can cause a phase delay 48 in sampling, shown in FIG. 3. The phase delay 48 may result in a sampling error and a degraded signal-to-noise ratio (SNR). If the sampling signal is asynchronous to the ADC clock, it may lead to kick-back at the input before sampling.